1. Field of the Invention
The present invention relates to the field of generation of timing pulses having precise delays and more particularly to synchronous delay lines as used in metal-oxide-semiconductor (MOS) integrated circuits.
2. Related Application
This application is related to copending application, Ser. No. 434,340, filed 11/13/89 and entitled "Synchronous Delay Line with Automatic Reset".
3. Prior Art
In an integrated circuit, having memory, processor, and/or other circuitry, it is necessary to have clocking or timing signals for various uses, such as latching of address signals, decoding the address signals and etc. One technique of generating "on-chip" timing signals is by the use of a synchronous delay line. Prior art techniques of utilizing a synchronous delay line are described in U.S. Pat. No. 4,496,861 entitled "Integrated Circuit Synchronous Delay Line" and in an article entitled "A Novel Precision MOS Synchronous Delay Line", IEEE Journal of Solid State Circuits, Volume SC-20, pp. 1265-1271, December 1985. The synchronous delay line is used to generate timing pulses designed to have precise delays from the start of a clock period. This particular synchronous delay line receives a clock reference signal and provides a series of taps, wherein each tap provides a timing pulse that has a precise delay from the commencement of a clock cycle which is initiated by the reference clock.
Although the synchronous delay line described in the above-mentioned prior art reference provides for on-chip timing signals having very high timing accuracy and which is also insensitive to variations due to processing, supply voltage and temperature, it has a disadvantage in that taps which are at or near either end of the synchronous delay line tend to have duty cycles which are either very small or very large in comparison to taps which are toward the interior of the synchronous delay line. Therefore, with the use of the prior art synchronous delay line as disclosed in U.S. Pat. No. 4,496,861, taps at or toward either end of the synchronous delay line are generally not usable for the purpose of generating delay signals.
As will be seen, the present invention provides for an improvement in which quadrature clock phases are utilized in order to effectively use the taps toward either end of the synchronous delay line.